The present invention relates to a semiconductor device and a manufacturing method therefor and, more particularly, to a semiconductor device, whose size in plan view is substantially equal to that of a semiconductor chip which is flip-chip-connected to a wiring pattern, and a manufacturing method therefor.
In recent years, reduction in size, thickness, and weight of semiconductor-applied products for use in mobile devices, such as digital cameras and portable telephones, has rapidly been progressed. Thus, e.g., miniaturization and density growth are required by semiconductor devices, such as NAND flash memories. A semiconductor device (see, e.g., FIG. 1) referred to as what is called a chip size package (CSP), whose size in plan view is set to be substantially equal to that of a semiconductor chip, has been proposed. Further, in addition to miniaturization and density growth, price-reduction is strongly required by such a semiconductor device.
Hereinafter, a semiconductor device and a manufacturing method therefor, which have hitherto been proposed, are described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view exemplifying a conventional semiconductor device. Referring to FIG. 1, the conventional semiconductor device 100 has a semiconductor chip 101, internal connection terminals 102, an insulating layer 103, wiring patterns 104, a solder resist 106, and external connection terminals 107.
The semiconductor chip 101 has a laminated semiconductor substrate 109, a semiconductor integrated circuit 111, a plurality of electrode pads 112, and a protection film 113. The semiconductor substrate 109 is a substrate obtained by separating a laminated Si wafer into individual pieces.
The semiconductor integrated circuit 111 is provided on a front surface of the semiconductor substrate 109. The semiconductor integrated circuit 111 is constituted by a diffusion layer, an insulating layer, a via-hole, and wiring (not shown). A plurality of electrode pads 112 are provided on the semiconductor integrated circuit 111. The plurality of electrode pads 112 are electrically connected to the wiring provided in the semiconductor integrated circuit 111. The protection film 113 is provided on the semiconductor integrated circuit 111. The protection film 113 is a film for protecting the semiconductor integrated circuit 111.
The internal connection terminals 102 are provided on the electrical pads 112, respectively. The top portion of each internal connection terminal 102 is exposed from the insulating layer 103. The top portion of each internal connection terminal 102 is connected to the wiring patterns 104. The insulation layer 103 is provided to cover one side of the semiconductor chip 101, on which the internal connection terminal 102 is provided. For example, a cohesive sheet-like insulating resin (e.g., a non-conductive film (NCF) or the like) can be used as the material of the insulating layer 103. Generally, such an insulating resin is formed of an epoxy resin, a cyanate ester resin, or the like, and has milk-white or colorless transparency. This insulating resin transmits alpha (a) rays, visible light rays, and ultraviolet rays to the semiconductor integrated circuit 111 placed under the insulating layer 103.
The wiring patterns 104 are provided on the insulating layer 103. The wiring patterns 104 is connected to the internal connection terminals 102. Each wiring pattern 104 is connected to an associated one of the electrode pads 112 via an associated one of the internal connection terminals 102. Each wiring pattern 104 has an external connection terminal provision area 104A on which an external connection terminal 107 is provided. The solder resist 106 is provided on the insulating layer 103 so as to cover apart of each wiring pattern 104 other than associated one of the external connection terminal provision areas 104A.
Each external connection terminal 107 is provided on the external connection terminal provision area 104A of an associated one of the wiring patterns 104. The external connection terminal 107 is connected to each wiring pattern 104. For example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu can be used as the materials of the external connection terminals 107.
FIG. 2 is a plan view exemplifying a semiconductor substrate on which the conventional semiconductor device is formed. In FIG. 2, reference numeral 110 designates a semiconductor substrate. Reference character C denotes a position (hereunder referred to as a cutting position C) at which a dicer cuts the semiconductor substrate 110. Referring to FIG. 2, the semiconductor substrate 110 has a plurality of semiconductor device formation areas A and a plurality of scribe areas B for separating the plurality of semiconductor device formation areas A. The plurality of semiconductor device formation areas A are areas on which semiconductor devices 100 are formed. The semiconductor substrate 110 is laminated and cut at the cutting positions C into semiconductor substrates 109 (see FIG. 1) described above.
FIGS. 3 to 11 are views exemplifying a process of the conventional semiconductor device. In FIGS. 3 to 11, sometimes, the same composing elements as the conventional semiconductor device 100, illustrated in FIG. 1, are designated with the same reference numeral. The description of such composing elements is omitted. In FIGS. 3 to 11, reference character A designates each of a plurality of semiconductor device formation areas (hereunder referred to as “semiconductor device formation areas A”). Reference character B designates each of a plurality of scribe areas (hereunder referred to as “scribe areas B”) for separating the plurality of semiconductor device formation areas from one another. Reference character C designates each of positions (hereunder referred to as “cutting positions C”) at which a dicing blade cuts the semiconductor substrate 110.
First, in a step illustrated in FIG. 3, a semiconductor chip 101 having a semiconductor integrated circuit 111, a plurality of electrode pads 112, and a protection film 113 is formed on a front side of a semiconductor substrate 110 which is not laminated yet. Subsequently, in a step illustrated in FIG. 4, internal connection terminals 102 are formed on the plurality of electrode pads 112, respectively. In this stage, there is variance in height among a plurality of internal connection terminals 102.
Subsequently, in a step illustrated in FIG. 5, a flat plate 115 is pressed against the plurality of internal connection terminals 102 to thereby uniformize the height thereof (i.e., leveling is performed thereon). Then, in a step illustrated in FIG. 6, an insulating layer 103 made of resin is formed to cover one side of the semiconductor chip 101, on which the internal connection terminals 102 are formed, and the internal connection terminals 102. For example, a cohesive sheet-like insulating resin (e.g., a non-conductive film (NCF) or the like) can be used as the material of the insulating layer 103. Generally, such an insulating resin is formed of an epoxy resin, a cyanate ester resin, or the like, and has milk-white or colorless transparency. This insulating resin transmits alpha rays, visible light rays, and ultraviolet rays to the semiconductor integrated circuit 111 placed under the insulating layer 103.
Subsequently, in a step illustrated in FIG. 7, the insulating layer 103 is polished until the top surface 102A of each of the internal connection terminals 102 is exposed from the insulating layer 103. Polishing is performed such that the top surface 103A of the insulating layer 103 is substantially flush with the top surface 102A of each of the internal connection terminals 102 at that time. Consequently, the top surface of a structure illustrated in FIG. 7 (more specifically, the top surface 103A of the insulating layer 103 and the top surfaces 102A of the internal connection terminals 102) becomes a flat surface.
Then, in a step illustrated in FIG. 8, a wiring pattern 104 is formed on the top surface of the structure illustrated in FIG. 7. More specifically, the wiring pattern 104 is formed as follows. That is, a metallic foil (not shown) is attached to the structure illustrated in FIG. 7. Subsequently, a resist (not shown) is coated over the metallic foil. Then, this resist is exposed and developed to thereby form a resist film (not shown) on the metallic foil coated on a part corresponding to an area on which the wiring pattern 104 is formed. Subsequently, the metallic foil is etched using the resist film as a mask. Thus, the wiring pattern 104 is formed (subtractive method). Then, the resist film is eliminated.
Subsequently, in a step illustrated in FIG. 9, a solder resist 106 is formed on the insulating layer 103 to cover a part of the wiring pattern 104, which is other than the external connection terminal provision area 104A. Then, in a step illustrated in FIG. 10, the semiconductor substrate 110 is polished from the rear side of the semiconductor substrate 110. Thus, the semiconductor substrate 110 is laminated. Subsequently, in a step illustrated in FIG. 11, an external connection terminal 107 is formed on the external connection terminal provision area 104A. For example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu can be used as the materials of the external connection terminals 107. Then, a plurality of semiconductor devices 100 are manufactured (see, e.g., Patent Documents 1 and 2) by cutting the semiconductor substrate 110 at parts respectively corresponding to the cutting positions C.    [Patent Document 1] JP-A-9-64069    [Patent Document 2] JP-A-2007-311828
However, in the case of using an alloy containing Pb as the material of the external connection terminal 107, sometimes, alpha rays are generated from a radioactive material, such as uranium (U) and thorium (Th), contained in Pb. The generated alpha rays are transmitted by the insulating layer 103. Then, the alpha rays travel towards the semiconductor integrated circuit 111. Further, the alpha rays reach the semiconductor substrate 109. The alpha rays having reached the semiconductor substrate 109 act upon a Si wafer and the like, which constitute the semiconductor substrate 109. Thus, electron-hole pairs are generated. Consequently, in the case of using an alloy containing Pb as the material of the external connection terminal 107, the conventional semiconductor device and the manufacturing method therefor have a problem in occurrence of what is called a soft error that is a phenomenon in which information is rewritten due to electric charges stored in a memory cell.
Further, even in the case of using an alloy of Sn and Cu, and an alloy of Sn and Ag, which are Pb-free materials, as the material of the external connection terminal 107, it is often that Pb is contained as an impurity in tin oxide used as the material of Sn. Sometimes, alpha rays are generated, similarly to the case of using an alloy containing Pb as the material of the external connection terminal 107. The generated alpha rays are transmitted by the insulating layer 103. Then, the alpha rays travel towards the semiconductor integrated circuit 111. Further, the alpha rays reach the semiconductor substrate 109. The alpha rays having reached the semiconductor substrate 109 act upon a Si wafer and the like, which constitute the semiconductor substrate 109. Thus, electron-hole pairs are generated. Consequently, even in the case of using an alloy of Sn and Cu, and an alloy of Sn and Ag, which are Pb-free materials, the conventional semiconductor device and the manufacturing method therefor have a problem in occurrence of what is called a soft error that is a phenomenon in which information is rewritten due to electric charges stored in a memory cell.
Further, the insulating layer 103 contains an inorganic filler, e.g., spherical silica (SiO2), in order to reduce the coefficient of thermal expansion. The inorganic filler contains an infinitesimal quantity of radioactive materials, such as uranium (U) and thorium (Th). Accordingly, sometimes, alpha rays are generated from a radioactive material, such as uranium (U) and thorium (Th), contained in Pb. The generated alpha rays are transmitted by the insulating layer 103. Then, the alpha rays travel towards the semiconductor integrated circuit 111. Further, the alpha rays reach the semiconductor substrate 109. The alpha rays having reached the semiconductor substrate 109 act upon a Si wafer and the like, which constitute the semiconductor substrate 109. Thus, electron-hole pairs are generated. Consequently, in the case of using such an insulating layer, the conventional semiconductor device and the manufacturing method therefor have a problem in occurrence of what is called a soft error that is a phenomenon in which information is rewritten due to electric charges stored in a memory cell.
Furthermore, the solder resist 106 contains an inorganic filler, e.g., spherical silica (SiO2), in order to reduce the coefficient of thermal expansion, similarly to the insulating layer 103. Accordingly, in the case of employing the solder resist 106, the conventional semiconductor device and the manufacturing method therefor have a problem similar to that of the insulating layer 103.